Centro Universitário FEI / CADENCE University Program Member
Coordenador/Coordenator/Responsable for the site: Prof. Dr. Salvador Pinillos Gimenez and Prof. Dr. Renato C. Giacomini
Integrated Electronics Devices
Electrical Enginner Department
Centro Universitario FEI
Av. Humberto de Alencar Castelo Branco, 3972 - Assunção
Sao Bernardo do Campo - Sao Paulo - Brazil - CEP 09850-901
Tel: +55 (0)11 4353 2910 (ext. 2184)
Fax: +55 (0)11 4109 5994
Email: sgimenez@fei.edu.br
Projeto: Projetos de Circuitos Integrados Digitais com Geração Automática de Leiaute Utilizando-se as Ferramentas CADENCE (Custom IC and Digita IC) – Prof. Dr. Salvador Pinillos Gimenez
Project: Digital Integrated Circuits Design with Automatic Layout Generation Using the CADENCE EDA Tools (Custom IC and Digital IC) - Prof. Salvador Pinillos Gimenez, PhD
O objetivo deste projeto é implementar o leiaute de circuitos integrados digitais de forma automática a partir de um arquivo VHDL/VERILOG, utilizando-se as ferramentas CADENCE. Além disso, uma meta bastante importante desse projeto é a formação de recursos humanos de alunos de iniciação científica, mestrado e doutorado na área de projeto/simulação/leiaute/fabricação de circuitos integrados utilizando-se as ferramentas da CADENCE.
The objective of this project is to implement automatically layouts of digital integrated circuits with the use of CADENCE EDA tools. Besides that, other very important goal of this project is the generation of human resources regarding scientific students, master students and PhD students in the design/simulation/layout/manufacturing of integrated circuits using CADENCE EDA tools.
Dois alunos de Mestrado (FILIPE ANTOINE KHATCHADOURIAN e VICTOR SIQUEIRA MARTINS BRAGA) trabalharam com as ferramentas CADENCE para a geração automática de leiaute de um microcontrolador 8051, conforme ilustrado na Figura 1.
Projeto finalizado em 2015.
Two Masters Students (FILIPE ANTOINE KHATCHADOURIAN e VICTOR SIQUEIRA MARTINS BRAGA) work with the CADENCE tools to generate automatically the 8051 microcontroller, as illustrated in Figure 1.
Figura 1. Leiaute do 8051 gerado com as ferramentas da CADENCE.
Figure 1. The 8051 microcontroller layout implemented with the CADENCE tools.
Others students will continue being trained with the CADENCE tools in order to design integrated circuits at FEI University Center (Centro Universitário FEI).
FEI University Center acknowledges CADENCE by the opportunity to participate of the University Program.
Project completed in 2015.
Projeto: Arquitetura de CPU Inovadora Focada em Sistemas de Tempo Real – Prof. Dr. Salvador Pinillos Gimenez.
Project: Innovative CPU Architecture Focused on Real-Time Systems – Prof. Salvador Pinillos Gimenez, PhD.
Este trabalho propõe uma nova técnica e arquitetura de hardware para controle de multitarefas em sistemas de tempo real (RTS) desenvolvidos para execução em microprocessadores ou microcontroladores de núcleo único. Tem como um dos objetivos implementar o leiaute de um processador digital de forma automática a partir de um arquivo VHDL/VERILOG, utilizando-se as ferramentas CADENCE. Além disso, uma meta bastante importante desse projeto é a formação de recursos humanos de alunos de iniciação científica, mestrado e doutorado na área de projetos, simulação, leiaute e fabricação de circuitos integrados utilizando-se as ferramentas da CADENCE.
This work proposes a new technique and hardware architecture for control of multitasking in real-time systems (RTS) developed to run on single-core microprocessors or microcontrollers. It has as one of its objectives to implement automatically layouts of one digital processor based on VHDL/VERILOG files with the use of CADENCE EDA tools. Besides that, other very important goal of this project is the generation of human resources regarding scientific students, master students and PhD students in the design/simulation/layout/manufacturing of integrated circuits using CADENCE EDA tools.
Um aluno de Doutorado (LEANDRO POLONI DANTAS) e um aluno de iniciação científica (YURI GABRIEL DORGAN IASBECH) trabalharam com as ferramentas CADENCE para a geração automática de leiaute de um microprocessador MIPS modificado, conforme ilustrado na Figura 1.
One PhD Student (LEANDRO POLONI DANTAS) and one scientific student (YURI GABRIEL DORGAN IASBECH) work with the CADENCE tools to generate automatically the layout of a modified MIPS processor, as illustrated in Figure 1.
Figura 1. Arquitetura do processador MIPS modificado.
O aluno de doutorado, LEANDRO POLONI DANTAS, continua trabalhando no projeto de um microcontrolador MIPS modificado, no qual ele está incorporando um sistema operacional de tempo real (Real-Time Operational System, RTOS).
The PhD Student, LEANDRO POLONI DANTAS, continues working to design a modified MIPS microcontroller, which he is incorporating a real-time operational system (RTOS).
A Figura 1 ilustra o leiaute final do circuito do microcontrolador IHM-Plasma, com destaque para suas dimensões e área.
Figure 2 illustrates the final layout of the IHM-Plasma microcontroller implemented by using the Cadence tools.
Fonte: Autor.
Figura 2 – Leiaute do microcontrolador IHM-Plasma.
Figure 2 – Layout of the IHM-Plasma microcontroller.
The Leandro Poloni Dantas will defende his PhD on May, 24 2018.
O aluno de iniciação científica (YURI GABRIEL DORGAN IASBECH) finalizou com sucesso o seu projeto de pesquisa, no qual leiautes de circuito integrado (CI) digitais podem ser gerados automaticamente através do uso das seguintes ferramentas: Quartus II (Verilog/VHDL) e da CADENCE
(RTL Compiler e Encounter). Projeto finalizado em Dezembro de 2016.
The scientific student, YURI GABRIEL DORGAN IASBECH, finished with success his research project, which layouts of digital integrated circuits (ICs) can be generated automatically through the use of the following
software tools: Quartus II (Verilog/VHDL) and CADENCE (RTL Compiler e Encounter). This project was finished in 2016 (December).
IGOR KRAUSE foi um aluno de iniciação cientifica e finalizou o seu projeto que foi um decodificador de 3 entradas e 8 saídas (Verilog/VHDL) e fez a geração automática desse leiaute utilizando-se as ferramentas da CADENCE, conforme pode ser visualizado na Figura 3. Finalizado em
2017.
IGOR KRAUSE was a scientific initiation student and he finished a project
of a decoder with 3 inputs and 8 outputs (Verilog/VHDL) and implemented
its layout by using the CADENCE tools, according Figure 3. Finalized in
2017.
Fonte: Autor
Figura 3 - Leiaute final do decodificador
Figure 3 – Final layout of the decoder
LUIS BINI foi um aluno de iniciação cientifica e finalizou os seu projeto de pesquisa relacionado a um multiplexador de 4 entradas e 16 saídas (Verilog/VHDL) e também implementou o leiaute desse projeto de forma automática utilizando-se as ferramentas da CADENCE, conforme pode ser visto na Figura 4. Finalizado em 2017.
LUIS BINI is another scientific initiation student and he finished his design of a multiplexer (mux) with 4 inputs and 16 outputs (Verilog/VHDL) and implemented its layout by using the CADENCE tools. Finished in 2017.
Fonte: Autor
Figura 4 - Leiaute final do multiplexador
Figure 4 – Final layout of the miltiplexer
Outros estudantes irão continuar a ser treinados com as ferramentas da CADENCE a fim de projetarem circuitos integrados no Centro Universitário FEI.
Others students will continue being trained with the CADENCE tools in order to design integrated circuits at FEI University Center (Centro Universitário FEI).
O Centro Universitário FEI reconhece CADENCE pela oportunidade de participar do Programa Universitário.
Projeto iniciado em 2016 e em andamento.
FEI University Center acknowledges CADENCE by the opportunity to participate of the University Program.
Project started in 2016 and ongoing.
Project: The next generation of non-standard layout styles for MOSFETs.
Prof. Dr. Salvador Pinillos Gimenez
The non-standard gate geometries [Hexagonal/Diamond, Octagonal: Octo, Ellipsoidal, Wave, Overlapping-Circular Gate (O-CGT), and Fish] for MOSFETs are capable of booting their electrical performance and the ionizing radiation tolerance simultaneously in comparison to those found in standard gate geometries (rectangular) MOSFETs counterparts, whose were already published in international journals and congresses. This happens due to the presence of the new effects in their structures already reported in the literature, such as the Longitudinal Corner Effect (LCE): responsible for boosting the resultant longitudinal electric field due to the drain to source bias in comparison to the one measured in the Rectangular MOSFET counterpart (same gate area, channel width, and bias conditions); PArallel connections of MOSFETs with Different Channel Lengths (L) Effect (PAMDLE): responsible for reducing the effective channel length (Leff) in relation to the one measured in the Rectangular MOSFET counterpart (same gate area and channel width); Deactivation of the Parasitic MOSFET in the Bird’s Beak Regions Effect (DEPAMBBRE): responsible for curving the resultant longitudinal electric field along of the channel length of the MOSFET and consequently electrically deactivating the parasitic MOSFETs of the Bird’s Beak regions [1-19].
In this context, I am proposing a new line of non-orthodoxy layout styles for MOSFETs which are more effectives and are able to further improving the electrical performance and the ionizing radiation tolerances of MOSFETs. These innovative layout styles are based in the hexagonal, octagonal, ellipsoidal, etc., but they present smaller dimensions in relation to the Diamond, Octo, and Ellipsoidal layout styles for MOSFETs already studied by my research group. Besides, I will study the electrical behavior of these new layout styles in comparison to the conventional (rectangular) MOSFETs. Furthermore, I will use them as unit (base) cells to implement Planar Power MOSFETs (parallel association of MOSFETs) which their electrical behavior will be compared to those of the multifinger (rectangular) Power Planar MOSFETs..
Projeto: Novo Amplificador de Bio-
Potencial Utilizando Pseudo-Resistor
Bipolar-MOS com Baixa Impedância
de Saída Diferencial
Prof. Dr. Renato C. Giacomini
A aquisição de sinais bioelétricos tem sido um desafio para os designers eletrônicos. Os sinais elétricos de baixo nível adquiridos pelos transdutores de eletrodos (de décadas de µV a alguns mV) estão associados a umacomponente intrínseca de CC criada pela associação eletrodo-eletrólito, que varia de 100 a 500 mV. Estes sinais são conectados através de um longo caminho para a entrada do amplificador (cabos, conectores), resultando em um problema crítico, envolvendo cancelamento DC e baixa relação sinal/ruído. Algumas soluções foram apresentadas em artigos utilisando o pseudo-resistor bipolar MOS com diferentes tecnologias e soluções de circuitos. Outros trabalhos com foco no pseudo-resistor foram publicados, para diferentes tecnologias (1,5µm; 0,5µm e 0.18µm), mostrando que as aplicações ainda estão em pesquisa, mas nenhuma na tecnologia BiCMOS de 0,13µm.
Este projeto pretende implementar uma nova topologia de bio-amplificador, partindo de resultados anteriores, obtidos a partir de circuitos anteriores, fabricados pela MOSIS na tecnologia BiCMOS 8HP 0,13µm. O amplificador utiliza pseudo-resistores bipolares MOS.
Situação atual: Foram produzidos amplificadores para deteção das ondas QRS, que estão em testes de laboratório. Na próxima rodada, serao produzidos circuitos completes dos amplificadores.
Project: Design of a New Bio-potential Amplifier Using MOS-Bipolar Pseudo-Resistor with Differential Low Output Impedance
Prof. Renato C. Giacomini, PhD
Bioelectric signal acquisition has been a challenge to electronic designers. The low-level electric signals acquired by the electrode transducers (from decades of µV, to some mV) are associated with an intrinsic DC component created by the electrode-electrolyte association, which ranges from 100 to 500mV. These signals are connected through a long path to the amplifier input (cables, connectors), resulting in a critical problem, involving DC cancellation and low signal-to-noise ratio. Some solutions have been presented in papers using the MOS-bipolar pseudo-resistor with different technologies and circuit solutions. Other works with focus on the pseudo-resistor were published, for different technologies (1.5µm, 0.5µm, and 0.18µm), showing that applications are still being researched, but no one with 0.13µm technologies in BiCMOS.
The present project intends to implement a new bio-amplifier topology, departing from previous results, obtained from partial circuits, which were assembled by MOSIS in BiCMOS 8HP 0.13µm last year. The amplifier uses MOS-bipolar pseudo-resistors.
Current situation: Some amplifiers were produced for QRS wave detection, which are in lab tests. In the next run, complete amplifier circuits will be produced.
Projeto: Modulador Chaveado de Amplitude SubGHz
Prof. Dr. Renato C. Giacomini
Este projeto implementa um modulador de modulação de amplitude Shift Keying – ASK usando a topologia Complementary Cross-Coupled LC Oscillator. São utilizados transistores nMOS e pMOS. A modulação está na faixa RF de 1GHz. O consumo de energia é de 10mW e VDC 2.5V. O indutor é implementado através de uma bobina.
No momento está em projeto uma nova versão, com amplificadores acoplados à saída de sinal.
Project: SubGHz Amplitude Shift Keying Modulator
Prof. Renato C. Giacomini, PhD
This project implements an Amplitude Shift Keying – ASK modulator using the Complementary Cross-Coupled LC Oscillator topology. Both nMOS and pMOS transistors are used. The modulation is in Sub 1GHz RF range. The power consumption of 10mW and VDC 2.5V. The inductor is implemented through a coil.
At the moment a new version is being designed, with amplifiers coupled to the signal outputs.
Projeto: Matriz para Discriminação de Comprimento de Onda com diodos PIN Laterais
Prof. Renato C Giacomini, PhD;
Prof. Rudolf, T Buhler, PhD
O conceito de diodos PIN laterais apresentado na figura 1 (a) é usado para implementar uma matriz (figura 1 b) que discriminará os comprimentos de onda de luz. O circuito APS (active pixel sensor) é apresentado na figura 1 (c), formado por 1 fotodíodo PIN, 1 transistor MOS para reset (RST), 2 transistores MOS para seleção de linha e coluna (SR e SC, respectivamente), 1 MOS transistor para amplificação de sinal (AMP), terminais de alimentação (VDD e GND) e o sinal de saída (VOUT). Os transistores SR e SC operarão em regime triodo (linear). O circuito APS será inserido em cada cátodo, conforme apresentado na figura 1 (d), e coberto por metal. Os dados recolhidos serão posteriormente analisados através de análise de discriminação linear.
Project: Wavelength Discriminant Lateral Gated PIN Diode Matrix
Prof. Renato C Giacomini, PhD;
Prof. Rudolf, T Buhler, PhD
The concept of lateral gated PIN diodes presented in figure 1 (a) are used to implement a matrix (figure 1 b) that will discriminate wavelengths. The APS circuit (a.k.a. PIN Cell) is presented in figure 1 (c), formed by 1 PIN photodiode, 1 MOS transistor for reset (RST), 2 MOS transistors for row and column selection (SR and SC, respectively), 1 MOS transistor for signal amplification (AMP), power supply terminals (VDD and GND) and the output signal (VOUT). The SR and SC transistors will operate in triode (linear) regime. The APS circuit will be insert in each cathode, as presented in figure 1 (d), and covered by metal. The gathered data will be latter analyzed through linear discrimination analysis.
(A)
(B)
(C)
(D)
Figure 1 – Basic schematic view of (a) a single lateral PIN diode, (b) the matrix structure, (c) APS circuit and (d) PIN cell inside the cathode.
Projeto: Amplificador de Bio- Potencial Utilizando Pseudo-Resistor Bipolar-MOS com Baixa Impedância de SaídaDiferencial e curto tempo de Recuperação
Prof. Renato C Giacomini, PhD;
A aquisição de sinais bioelétricos tem sido um desafio para os designers eletrônicos. Os sinais elétricos de baixo nível adquiridos pelos transdutores de eletrodos (de décadas de µV a alguns mV) estão associados a umacomponente intrínseca de corrente contínua criada pela associação eletrodo-eletrólito, que varia de 100 a 500 mV. Estes sinais são conectados através de um longo caminho para a entrada do amplificador (cabos, conectores), resultando em um problema crítico, envolvendo cancelamento DC e baixa relação sinal/ruído. Algumas soluções foram apresentadas em artigos utilizando o pseudo-resistor bipolar MOS com diferentes tecnologias e soluções de circuitos. Outros trabalhos com foco no pseudo-resistor foram publicados, para diferentes tecnologias (1,5µm; 0,5µm e 0.18µm), mostrando que as aplicações ainda estão em pesquisa, mas nenhuma na tecnologia BiCMOS de 0,13µm.
Este projeto implementa uma nova topologia de bio-amplificador, partindo de resultados anteriores, obtidos a partir de circuitos anteriores, fabricados pela MOSIS na tecnologia BiCMOS 8HP 0,13µm. O amplificador utilizapseudo-resistores bipolares MOS.
Foram projetados e fabricados amplificadores para detecção das ondas QRS, que estão em testes de laboratório.
Project: The “Second Generation” of Non-Standard layout styles for MOSFETs. 2x2
Prof. Dr. Salvador Pinillos Gimenez
Several publications on journals and international congresses have shown that the non-standard gate geometries [Hexagonal/Diamond, Octagonal: Octo, Ellipsoidal, Wave, Overlapping-Circular Gate (O-CGT), and Fish] for MOSFETs are capable of booting their electrical performance due to the LCE and PAMDLE effects, and the ionizing radiation tolerance due to the DEPAMBBRE effect, simultaneously, in comparison to those found in standard gate geometries (rectangular) MOSFETs counterparts [1-19].
In this context, I have manufactured several MOSFETs with the non-standard gate geometries (Half-Diamond MOSFETs, Half-Octo MOSFET, and Half-Ellipsoidal MOSFETs) of the “Second Generation” of innovative layout styles for MOSFETs by using the 180 nm Bulk CMOS ICs technology from TSMC. The main characteristics of these MOSFETs is that they present smaller channel lengths of the “First Generation” (Diamond MOSFET, Octo MOSFET and Ellipsoidal MOSFETs) and consequently the LCE and PAMDLE effects in the MOSFETs of the “Second Generation” tend to be more intensive than those observed in the First Generation and therefore these innovative layout styles for MOSFETs can further improve their electrical performance and further reduce the die area of these devices and of the analog and radio-frequency CMOS ICs, as illustrated in Fig bellow.
Besides, the MOSFETs manufactured with the innovative layouts styles of the “Second Generation” continue to present the DEPAMBBRE effect and consequently they will continue to present improved “Total Ionizing Dose” (TID) tolerances than those observed in the standard MOSFETs.
These innovative MOSFETs with the “Second Generation” have been studying by experimental data by me and by my students (Scientific Initiation, Master and PHD) and their electrical behavior will be compared to the conventional (rectangular) MOSFETs and those of the “First Generation”. Furthermore, I will use them as unit (base) cells to implement Planar Power MOSFETs (parallel association of MOSFETs) which their electrical behavior will be compared to those of the multifinger (rectangular) Power Planar MOSFETs.
Project: Differential Bio-Amplifier Circuit for Bio-Signals
Prof. Dr. Renato C. Giacomini
A differential bio-amplifier circuit using the pseudo-resistor previously proposed. The pseudoresistor is used in the feedback network of bio-amplifiers to eliminate low frequencies and DC levels that can disturb the bio-potential acquisition. The use of pseudo-resistor sets the lower-cutoff frequency with the advantage of using smaller die area when compared to regular resistors and allows faster recovery times.
Basic schematic view of the lateral gated PIN diode frequency sensor.
Current status: In the development phase, the circuit will be produced.
Project: Bio-Potential Amplifier Using Bipolar-MOS Pseudo-Resistor with Low Differential Output Impedance and Short Recovery Time
Prof. Renato C Giacomini, PhD;
The acquisition of bioelectric signals has been a challenge for electronic designers. The low-level electrical signals acquired by electrode transducers (from decades of µV to some mV) are associated with an intrinsic component of direct current created by the electrode-electrolyte association, which varies from 100 to 500 mV. These signals are connected through a long path to the amplifier input (cables, connectors), resulting in a critical problem, involving DC cancellation and low signal / noise ratio. Some solutions were presented in articles using the bipolar MOS pseudo-resistor with different technologies and circuit solutions. Other works focusing on the pseudo-resistor have been published, for different technologies (1.5µm; 0.5µm and 0.18µm), showing that the applications are still in research, but none in the 0.13µm BiCMOS technology.
This project implements a new bio-amplifier topology, based on previous results, obtained from previous circuits, manufactured by MOSIS using BiCMOS 8HP 0.13µm technology. The amplifier uses bipolar MOS pseudo-resistors.
Amplifiers were designed and manufactured to detect QRS waves, which are in laboratory tests.
Current status: Amplifiers were produced to detect QRS waves, which are in laboratory tests. In the next round, complete circuits of the amplifiers will be produced.
Project: Pseudo-Resistor structures without external polarization of door
Prof. Dr. Renato C. Giacomini
With a focus on the evolution of bio-potential amplifiers, new pseudo-resistor topologies were designed and sent for manufacturing. A model implemented in SPICE is in the final stage of implementation and new experimental data from these devices will assist in its development.
Current status: New pseudo-resistors are being manufactured for the evolution and development of the SPICE model.
Project: Discrimination of wavelengths and optical power in a 2x2 Pixel sensor
Prof. Renato C Giacomini, PhD;
The lateral PIN photodiodes with door and multidedos, manufactured through the agreement with MOSIS and IMEC, and shown in the following figure was developed to discriminate conda lengths of the RGB light spectrum with multiple light intensities.
Use of a reset APS circuit to sample and maintain and amplify the photocurrent, in a 2x2 Configuration for the acquisition of the photocurrent level and a line / column selection circuit composed of 2 type D Flip-Flops.
Full layout developed:
The same concept of PIN photodiodes with side door as before is used to implement a matrix that will discriminate wavelengths and light intensity:
Current status: Circuits for detecting wavelengths were produced. Electrical characterizations will be performed.
Project: Finite State Machine (FSM) capable of recovering after an electromagnetic interference
Prof. Renato C Giacomini, PhD;
The objective of this proposal is the fabrication of a semiconductor device for study and evaluation of digital architecture techniques. These techniques were studied during the master’s degree course and were subject for a dissertation. The study focused in means to build a Finite State Machine (FSM) capable of recovering after an electromagnetic interference, as a power supply noise, that could change the state of a flip-flop. The proposed device shall be composed of two FSM and an interface hardware to support the tests and verifications.
In the device, one FSM shall use the studied digital architecture techniques and the second shall be build using conventional digital circuitry. The interface logic will provide the data input and output for the FSMs, as well as a glitch detector to record the error events. The interface is also useful to reduce the external pin count, handling all data serially.
The device shall use around 12,000 transistors and 7 pads for power supply and interface signals. The figure below illustrates the structure of the device.
The glitch detectors are a new design motivated to build a library of reliable digital test circuits that can be used in other ICs. This can be an important tool for students to verify their designs using simple serial interface, similar, but not equal, to the well-known JTAG. The error event capture registers shall be doubled to enable the detection of an error in the capture registers. The valid errors, detected from state machines, must appear in both capture registers.
The serial interface enables low pad count. This design will use 4 pads for serial interface and 3 pads for power supply. The serial interface, I/O registers and Capture registers shall use a unique power supply line, while the FSMs will use a separate one. This allows noise injection in the FSM power supply and keep clean the power for the interface circuit.
The libraries generated by this work shall be made available for other students to use in their designs.
Current status: In the development phase, the circuit will be produced.
Project: Sensing of mechanical deformations
Prof. Renato C. Giacomini, PhD
Circuit developed to analyze the induced mechanical stress, in the frequency domain:
And its respective layout:
Current status: Circuit designed and manufactured. Electrical characterizations will be performed.
Project: SubGHz Amplitude Modulator Shift Keying
Prof. Renato C. Giacomini, PhD
This project implements an Amplitude Shift Keying (ASK) modulator using the Complementary Cross-Coupled LC Oscillator topology. Both nMOS and pMOS transistors are used. The modulation is in the Sub 1GHz RF band with power consumption of 10mW and VDC of 2.5V. The inductor is implemented through a coil.
Current status: A new version is being designed, with amplifiers coupled to the signal outputs.
Project: Sensing the Effects of Unique Particle Radiation Events (SEE)
Prof. Renato C. Giacomini, PhD
Heavy ion radiation interferes with the response of the device, causing it to malfunction. Developed in partnership with the CITAR Project, the Single Event Effects detection matrix is presented below, manufactured using GF BiCMOS 8HP 0.13 technology:
Current status: Circuit designed and manufactured. Electrical characterizations will be performed.
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Last updated: May 21, 2020. Copyright of these papers, reproduced here for timely dissemination of research information, is with the respective publishers.
